The present invention is applicable in manufacturing various types of semiconductor devices, which comprise a semiconductor wafer substrate, usually of doped monocrystalline silicon (Si), having at least one active device region or component (e.g., an MOS type transistor, a diode, etc.) formed thereon, and a plurality of sequentially formed inter-layer dielectrics (ILDs) and patterned conductive interconnect layers. With the above mentioned components, an integrated circuit is formed containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnection lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced metal layers are electrically interconnected by a vertically oriented conductive metal plug structure known as a “VIA.” A via is formed in the ILD separating the metal layers, while another conductive plug filling a contact area hole establishes Ohmic contact with an active region, such as a source or drain region of an MOSFET formed on the semiconductor substrate. Conductive lines formed in groove or trench—like openings in overlying dielectric layers extend substantially parallel to the semiconductor substrate and may include five or more metal levels in order to satisfy device geometry and scaling requirements.
In sub-micron process technologies, automated router tools are used to produce the physical routing structures in the metal layers. However, a number of design constraints limit the wireability of many chip designs due to redundancy requirements and various post processing steps intended to increase manufacturing yield. For example, to reduce the incidence of non-planar metal shapes in a design, a wide wire may be decomposed into several narrower wires. Post processing steps may include “cheese” and “fill,” which address manufacturing problems associated with non-planarity and metal density. EP 0 982 774 describes a problem known as “dishing,” which occurs in wide metal shapes. Dishing is a condition where an indentation, depression or dip is formed in the central portion of the wire. In the case where a wire shape includes a large lateral extension, the solution proposed by EP 0 982 774 replaces the wide wire with a plurality of narrower wires to achieve improved planarity of the wire surfaces. For some cases the narrower wires have lateral extensions that are still quite large and may still be characterized as “wide” wires for a given process technology. However, decomposition of a wide wire into a plurality of narrower width wires consumes additional wiring channels because the same overall current density and electro-migration requirements must be met for the decomposed wire.
Of course, the routed metal structures become more complex as more wires are routed per unit area. In many current designs, the majority of internal signals are routed using narrow single width wires. Consequently, new technical problems in manufacturing emerge in far smaller scale than mentioned above in context with EP 0 982 774. Very often the above-referenced metal shapes in a given plane are quite irregular in sub-micron process technologies. Those skilled in the art recognize that an irregular routing structure in small geometries is detrimental to manufacturing yield. This is due to optical effects, which reduce the resolution of the wire edge shapes. This is particularly true of wire ends, corners, or in metal shapes having complex geometries included in the routing structure. In short, manufacturing yield improves dramatically when metal layers exhibit uniform and predictable layout patterns. Accordingly, EP 0 982 774 does not address the critical manufacturing concerns associated with current process technologies.
One ideal solution would be to cover every routing track with a wire of identical width and spacing to its neighbours, thereby creating very regular metals structures. This, of course, is not possible as it would defeat the very purpose of routing a chip, which is to connect certain pins with each other, without creating electrical connections to pins that are not meant to be connected to a given wire.
FIG. 1 depicts a schematic zoom view of an exemplary section of chip wiring, in which the wiring structure shows wide wire 10, first signal wire 12, and second signal wire 14. All wires are arranged in parallel to each other. In general, wide wire 10 is typically about 50 times wider than the narrow signal wires 12 and 14. Two empty wiring tracks 16E-F are depicted adjacent to wires 12 and 14, and shown in FIG. 2 as fill shapes 21-23, as discussed infra.
FIG. 1A illustrates an isolated section of a wiring grid with wires 10, 13 and 14; wiring channels 16A-D; and spaces between wires 15. The term “wiring” is meant to comprise any collection of wire elements. A single “wire” is understood to be a single segment and mostly longitudinal conductive layer. The narrowest width wires for a given process technology and yield requirement form a characteristic geometric unit defined in the design ground rules for chip wiring. Such wires are considered as “single” objects, and are referred to as “single width wires,” which are depicted as 12 or 14 in FIGS. 1 to 6. Wide wires may also be defined as, for example, wire 10, which is intended to be a “double-wide” wire as compared to wire 12.
Wiring tracks 16A-F represent imaginary lines associated with the physical wire shape—whether for a single width wire or larger. The wire tracks typically form a grid having constant minimum space between adjacent wire pairs as defined in the design ground rules for a given process technology. The grid layout of the tracks corresponds to the maximum attainable density for single width wires. However, wide wires, such as wire 10 consume multiple wiring tracks.
A wire grid consisting of an array of single width wires exhibits identical spacing between adjacent wires as shown in FIG. 1A. Wire space 15 represents the minimum space allowed between the edges of adjacent wires 12 and 14. The separation between adjacent, parallel wirings tracks is often twice the width of the wire as measured from the centerline to centerline of the wire tracks. The wire pitch is defined as the minimum distance between adjacent wire tracks.
FIG. 2 shows a prior art approach to eliminating irregular routing structures that fill up unused wiring tracks 16 with “fill” patterns, which are sometimes connected to ground or to the supply voltage. In FIG. 2, the wiring shapes include fill patterns 21-23, to illustrate how fill shapes are combined with wire shapes to achieve uniform density in regions of the metal layer where not all wiring channels are utilized for signal routing.
The drawback of the approach shown in FIG. 2 is that fill patterns 21-23 may add switching capacitance to signal wires 12 and 14 and therefore increase the signal propagation time for the adjacent signal wires. Another disadvantage in the case of grounded fill patterns, is that shorts between signal wires and the adjacent grounded fill patterns can lead to a physical defect on the chip, which can limit manufacturing yield.